-   1806/1801 VM2


18062:

	16-ࠧ來  ய    PDP11-ᮢ⨬  ⥬  .
孮 CMOS.
᪠ ⢨ 譨 䠪஢:

-堭᪨ 䠪:
	ᨭᮨ쭠  1-5000 400/(*)=40g
	᪨  50-10000 㪮 
	(⭮⥫쭮 2-5 ) 170 ;
	堭᪨ 㤠 筮 ⢨ max 1500g ⥫쭮
	⢨ 0.1-2.0
	堭᪨ 㤠 ⭮ ⢨ max 150g 1-5,
	 ᪮७ 500g
-᪨ 䠪:
	ࠡ祥  1.33-4(10-6 ...)-3.
	⥬ । -60..+125 ࠤ.
	  ᯮ   +35 ࠤ. 98%
	᮫ﭮ (᪮) 㬠
	⬮ ஢ ᠤ(,)
-᪨ 䠪:
	᭥ ਡ

쭠 ࠡ⪠   50 000 ᮢ
⠭ +5+-10%, ॡ塞 譮 25 .
64-뢮 ⠫ࠬ᪨  ⨯ 18.64-2
.481.005 .
஢  뢠-2
77 ,  :
-  権
-EIS Extended Instruction Set
-FIS Floating Instruction Set if system ROM is able to emulate
⠪⮢  0-5 
ॣ஢ ᫮  5 1.2 
ॣ஢ 㬭  5 18 
ॣ஢   5 25 
U.max=6
0<U<U
 㧪   100 
⥬ ࠫ ᮮ⢥ ⠭  (QBUS)


	:

1	 ᨫ⥫ AD 0-15  SEL
13-11,	16 㭠ࠢ 室-
6-2,	室 設 -
63-60,	 AD 0-15:
53-50	᪠  -  ஢
14,15	WRQ1,WRQ2-室 ᨣ   墠 ࠫ,
	 १ .    ஢.
16	WACK-室 ࠧ襭 墠 ࠫ १ .
	襭 - ஢.( 稨  ஢
	࠭ 뤠 WRQ    ନ)
17	DMR-室 ॡ אַ 㯠(L)
18	SACK-室 ⢥ত 祭   אַ (L)
19	DMGO-室 ࠧ襭 אַ 㯠(L)
20	CLCO-室 ७ ⠪⮢ .  CLCI  让
	প  ⮩  䠧.
21	CLCI-室 ⠪⮢ ᮢ  0  5 :  ᪨.
22	U3 + ⠭
27	RPLY-室 (L)
28	DOUT-室 (L)
29	WTBT-室 (L)
30	 ७ 㧫 
31	SYNC-室 (L)
32	U2 + ⠭
33	DIN-室 (L)
34	AR-室  (L)
35	IAKO-室 ࠧ襭 뢠(L)
36	ACLO-室 ਨ ⥢ ⠭. ⥫ ஭
	뢠 ணࠬ   24.
	⥫ ஭ 樨 யணࠬ 
37	DCLO- ﭭ ⠭.  ஢ ࠭᫨
	 INIT  ਢ   砫쭮 ﭨ.
44	INIT-室  譨 ன(L)
45	VIRQ-室 ॡ ୮ 뢠(L)
46	HALT-室 室  ⮢ ०(L)
47	EVNT-室  뢠  ⠩  ⥫쭮
	஭.  100 ନ ஬
48	WIR-室 ॡ 뢠    ⥫쭮 ஭.
	᪨㥬,  250
49	SEL-室 饭  ⮢   ᭮ ॣ(L)
	   䠧 뤠  롨ࠥ ⥬ ,
	  ६  DIN 롨ࠥ  ॣ
64	U1 + ⠭
7,8,9,23,24,25,26,38,39,40,41,42,43,54,55,56,57,58,59-

	 ⮨  ᫥ :

樮 			()
 யணࠬ ࠢ	()
 ७ 䬥⨪		()
 뢠				()
 ࠡ⪨ ᫮ ⢫	()
䥩 			()


 ⠢  室:   ॣ    (),  ॣ    (),
ॣ    稪     (PC'),        ᮢ    (),
  ॣ      (  ),  ॣ        (    ),
  ⠭,  ॣ  ﭨ     (PSW),        ॣ
ﭨ    (PSW'),  ॣ    饣    祭    (R0..R7),
    (),    ॣ    筨    (),    16-ࠧ來    ,
ᤢ⥫  (),      ⮢    奬    (      凯).
    ਭ      譥  .        譥   
        ⠢        ।.        ॣ    
뢠  ନ஢        ।            ⥬
ࠫ    .  ᪮           ந室    ਥ
   ०,        믮  ⥪饩    ᫥
㦥  ਭ    ,             㦥        ணࠬ
஢.    ᯥ祭              ᫥饣    
  ᫮    ॣ    稪          .
  PC'  ࠭    ᫥饣         ᫮,    ..    PC+2.
।  横                ࠢ    ஬    
ᮤন PC'      砥  ࠢ⢠  ᫥  砭    ந室
⥭          PC',  ..  ந室        ਥ
᫥饩  .    ਭ  ᫥         믮.
楤    ୮    ⥭    ந室    ⭮-யணࠬ.
  ﭨ       ॣ        ॣ    ﭨ
㦨    ࠭  ਧ  (ﭨ),  ॡ뢠      
믮  権.    ॣ  PSW'  ࠭  ᫮  ﭨ   
ࠡ⪥    뢠.                  ॣ஢,
ᥬ         㯭    ணࠬ        ॣ    饣
祭.  ⠢訥      -            ॣ    筨
ᯮ  ஬    ஬筮  ࠭    ଠ樨    
믮             㯭    ⮫쪮    யணࠬ.
    奬  ᪮७   ७,        ன    ७
࠭  ᫥⥫쭮    ,  祬   १        ࠧ鸞.
    १      ᤢ⥫,              ᤢ
ந室  ᤢ  ࠭       ࠧ    ࠢ            
ᮤন       ନ஢    䬥᪮        横᪮
ᤢ.    ᤢ  ᫮    .  ᫥  ᤢ⥫   砥
⥫  १  樨,    뢠       ᯥ樠
ॣ.     ⮬    稢    䠧    ⥭    横    믮
ப.    横    믮   ப    ଠ    
ॣ,    ஬  ࠭  १   樨,    㯠    १
    ⮢    奬  .         ⠬    
᫮    믮    SWAB.    ⠪  ᯮ    뤠
襣       ⮢    .        ᯮ짮    
  ࠧ  ७  設          ⥭    ᮢ頥
    ⥭    横              横
⥭,    祬   㬥蠥    横    믮    ப.
	奬  ନ஢   ﭨ    ()        ᭮    ᨣ,
室    ,    ᤢ⥫            ७    䬥⨪
ନ ਧ १ 樨  N,  Z,  V,  C,    
  ᫮  ﭨ     ⥬    ᯮ            ⢫.
	   ७    䬥⨪    ।祭        ⭮
প  믮    㬭,   ,        ࠬ᪮
ᤢ MUL, DIV, ASH,  ASHC.    믮  ᮤঠ⥫쭮    
ᯮ        ப    ,             
।        奬    ࠢ          ७
䬥⨪        믮    樨.            
믮    ।  ᫮  ⠪⮢.  ७   ॣ    
७    䬥⨪    㯭                  ப.


	⮩        ᨭ஭樥    㣨     ࠢ
  ᨭ஭樨    .  ᫨    ᨣ   ମ,        
᪠  ᨣ  ⮢  .           ⠭    
砥    ਥ        ᨣ        "    ",
  ࠡ⪨   ﭨ        ᨣ        "    ﭨ",
    ࠡ⪥    뢠    ᨣ  ମ      .
    "ਭ  뢠"   ,    ,    ,    ࠡ뢠    
⥫  ப    (ᮤঠ饩    190    ᪨    ந).
	  뢠  㦨    ਥ    ।⥫쭮   ࠡ⪨
ᨣ  뢠.      室      ⭮    প
믮      RESET.            室:    ॣ    筨
뢠,  ,        1     2        ᮤঠ    30
᪨  ந,  9-ࠧ來   稪,        ࠢ    
ᨭ஭樨.    ᨣ  뢠  㯠    ॣ   筨
뢠.    믮    WAIT    ਣ    ""        
⠭    ᯥ樠쭮   ଠ    ப    யணࠬ.
    ᨣ  뢠  㯠        .      
ॠ  奬  ਮ  뢠.  ᫨  ⠢    ६
  뢠,     ᭠砫    㦨    뢠        訬
ਮ⮬.  ᫨  7-  ࠧ  PSW  ⠭    ,   譨    
⠫  뢠  ᪨.           ࢠ    ६,
ਭ    ᠭ,      ନ஢    ᨣ    INIT    
믮       RESET    㦨    9-ࠧ來    稪.    稪
᪠  ᨣ  DIN    DOUT     ᫥    ᠭ    
யணࠬ    믮        RESET.        ⨦
稪    㦭    祭    ᫥    奬       ࠢ.
	䥩     㦨        ࣠樨        
஬    ன⢠    ⥬  ࠫ.        䥩᭮
  ᮤন  ࡨ  אַ  㯠     ,    ᮢ饭    
奬    .  ࡨ  אַ  㯠   ᫥    㯫
    אַ   .    ᫥    㯫        
稢 ⥪騩  横      뤠  ࠧ襭    אַ  .
  ६  אַ  㯠    ⠭.  ᫥    ᫥
          ॣ      䥩     㯠
    .  ᫨    ⥬    ࠫ,        ⥫쭠
ࠫ,  墠祭  १  ,  ᢮,      稭    뤠
     ࠫ.
	    ।⢠    ४樨    䥩,    騥
  ६  ࠬ  䥩            譨    奬.
     ७    ⥬        ⥬    ॠ樨
4  ⥫      ⥬    (⮩)    .    
⥬    짮⥫᪮            ४뢠.    ⥬
    㯭    ⮫쪮              ᯥ樠        .
	  ਭ       ०.        ਥ
 ஥  ⠪,        믮    ᫥  
㦥 ਭ      ॣ  ,    稭  ਥ    
.    믮     ,    㦠    PC,    ⭮
⢫    ਥ  ᫥饩  .       ⠭
०    ⮩        ⠢    ਥ        
.  襭  ०  ந室    ⮣,        稪
  ⠥    ,    .           樥
    稪    ⠪  நo  ⠭  ०
⥬  ࣠樨  ⥭    ᫥  .       
᪠,  ᫨    ਭ         ॣ        
⠭  ਧ  ⮣,       ।        稫.    
᫥  ப    ᪠    뢠,        ᫨
  ᪨஢  뢠,     ᪠    யணࠬ


ࠡ⪨  뢠.  ᫨        ப       ਧ
饭    ⥬   ࠫ,    樮        ࠡ뢠
ᨣ      ,  㯠騩       䥩    .    ᫨
⥬  ࠫ  ᢮,    䥩        믮    横
  ࠫ,    樮        ६    믮
ப,    易        易    ⮢    
᫥饬  .

		ਭ樯 ࣠樨 䥩  ᭥ 
			  ६ ࠬ.

	⠭  SYNC      ஢        ᮮ頥,    
 ⠢    ⥬  ࠫ.      ᭨    
  த,      室  AR               
஢.   楤  ⥭  ⠭  DIN      ஢  
ᮮ頥,    뤠    祭    ⮢  ਥ       
.  楤  ⥭    த       ,        
室  RPLY        ஢.   ਧ    砭    
  ⠭  ஬  ᨣ  DIN      ᮪    ஢.    
楤    ਧ            ࠫ    
⠭    ஢       室    DOUT.            
த,      RPLY           ஢.    ਧ
砭        ⠭        DOUT    ᮪    ஢.
	  稭        ⮫쪮    ⮣,        ᢮
ࠫ.  ਧ   ⮣,        ⥬    ࠫ    ᢮,
    稥    室  DMR,  SACK,  AR,  RPLY  ᮪
஢.  ਧ  ⮣,    ᢮  ࠫ,    १  ,
          稥    ᮪    ஢        뢮
DMR, SACK, AR, RPLY, WACK.
	᫨      ࠡ           ⠭,    
ᯮ짮  ⠭  ᨣ  DMR      ஢.        ⮬
  믮      ⥪騩           ⠭.    ᫥
⠭    室  DMR   ᮪    ஢        த
믮      窨  ⠭.    ⠪  ⠭    짮
⥬  ࠫ  ,  ᪮    㤥    ঠ    
設  ⨢  ᮪  ஢.  ⮡         짮
ࠫ    ६  ⠭,  筮  ᫥     ᨣ    DIN
  १  1/2    ᨣ  CLCO  ᫥    ᨣ    DOUT    ⥪饣
      室  SACK    ஢.        ⮬    ,
稢  ⥪騩  ,  ⠭,      ᥬ  室,  ஬   CLCO,
DMGO,  SEL,  IAKO,  ३      ﭨ.    ⠭   
室  SACK  ᮪  ஢  믮  ணࠬ  㤥   த    
窨  ⠭.    ⠪⮢    ,    㯠        CLCI,
ᨭ஭  ࠡ            ࠭᫨  
ன প    CLCO.  ਥ  室    뤠  室  ᨣ
ਢ뢠    ७     ᨭ஭樨            쭥襬
ᬠਢ  ⭮⥫쭮  ᨣ  CLCO.    DMR,  AR,  WACK    
।      ஭⠬  ਭ    䠧    ஢   CLCO.
  RPLY  ਭ    䠧  ᮪  ஢.        SACK    
।  ஭  ਭ  ᨭ஭,          䠧  
஢   CLCO.            ࠡ⠥        묨    譨
ன⢠,  ਬ     ,    室騬                
஬,    ⨦  ᨬ쭮  த⢨  㦭    뤠
ᨣ  AR    RPLY    ᮣᮢ            ਥ        .
	  DMR      SACK    ᯮ        楤    ।
ࠢ    אַ  ,    WACK  -      楤    㯠    
⥫쭮  ࠫ  १  ,         த⢨    ⥬


  .   ⥫쭮    뤠            ᭮    
ॣ㫨   ᨣ    AR.    ⮡        䠧    뫠    쭮
⥫쭮, ᨣ  AR  㦭  ⠢    ஢    ⮩    䠧
ᨣ  CLCO,    ன  ᨣ  SYNC  室           ஢.
᫨    ॡ  믮,        ன    প
⭮⥫쭮  ⥫쭮  ஭  AR  ᭨            ࠫ.
	      ᭮    砭  ⥪饣   横    
室      ந室  .    祭    ᨣ    RPLY
  ஢    믮  楤  ⥭           
᭨ ᢮ ᨣ DIN,  DOUT,  SYNC  ᨬ    㯫  ᮪
஢  ᨣ  RPLY.  ᫨    ६  ⥪饣  横      
ନ஢   ᫥騩  横        ⮬      
,  ᨣ AR        ⮣,      ᭨  ᨣ  DIN
  DOUT,      ᨬ      ᨣ   RPLY    ⠢
  ᫥饣  横    ६    ⨥   ᨣ    SYNC
⥪饣   筥  ᫥騩  .    ⮬  砥,  ᫨  RPLY  
稢襣       ,        AR        砢襣    
⠭,          ⠢    ᨣ    DIN        DOUT    
ᮮ⢥饩    䠧  ਢ離    CLCO  ⮫쪮  ᫥    RPLY  
।饣  .  ᫨      ନ஢      ᫥騩
  祭  ⥪饣  横  ,        ६  襫  
  אַ      ,  砫  ᫥饣   横        㤥
  ⮫쪮   ﭨ  ᨣ  AR,        ﭨ  ᨣ
RPLY  稢襣      אַ  㯠.    ᫨        
⥪饣    AR  ᭨      ᨣ  DIN    DOUT,   
᫥騩    筥  ⮫쪮  ᫥  ⠭  AR    RPLY    ᮪
஢.
	砫  ᫥饣        楤ன    ਥ        
뢠    ।  ᮪    ஢        뢮    RPLY.
	᪮    ।    ᫥騩        稭
ᨬ    ﭨ  ᨣ    室  RPLY,            প
᪠    짮  ⨬  ᨣ  .     ⮩    楫
  ᯮ짮  প    ᨣ    AR.    ᫨    ⨥    AR
ந      ᨣ  SYNC,        ந    ⥫쭠
প  ᫥饣        ਮ  ⠪⮢  .    
  ६  ࠬ  ਢ           譨    ன
(ᨬ쭮 த⢨).
	     ᯥ樠    楤    ᭮    ⥭
(ᨭ஭  ).    믮    砫쭮  ᪥       ⥭
᫮,      ᯥ樠쭮  .  ᫨    横  ।饣    
ᨣ AR  (  RPLY    ७    )  뫨      
ᨣ SYNC,     ᭮  ⥭  १  1/2  T  CLCO  ⭮⥫쭮
ᨣ  SYNC    ⠢  ᨣ  DIN,SEL,          ६
⠭    AD0-AD15  ०  室.  SYNC    ⮬    ⠥    
᮪  ஢.  RPLY     ᯮ.    ⥫쭮    䠧    
஢  DIN,SEL  ⠢  ᥣ  2.    ᯥ祭    ਥ
ଠ樨    ன⢮    ⠢         設    
, 祬 १    ᫥  ஭  CLCO,    ஬  뫨  뤠  DIN  
SEL.  ᫥    DIN    SEL    १  /2  ⠢    設
⨢  ᮪  ஢    .  ᫨      ᨣ  DIN    
祭      אַ  ,    ᫥   ॢ    ࠫ    
⨢  ᮪    ⠢    ࠫ      ᫥饣
, ᫨  ନ஢ ஬.
	᭮  ⥭  ਬ    ⥭    祩        
ॣ  譥  ன⢠.    砭  뤠        
⠢  DIN    ஢    ६  ⠭       設
० 室. ᫨   64    ᫥  ⠢  DIN    RPLY    


  ஢,    ॢ    ᮪  ஢  SYNC    DIN   
뢠    ᠭ.  ᫨  RPLY  襫   ६,        
믮  ⥭    뢠  DIN       SYNC.    ⮡    ६    
⠭  RPLY    ᮬ  DIN  뫮  訬,        ᨣ    RPLY
⠢       䠧  ᮪  ஢  CLCO.    
ਥ      ⠢     ,    祬    १    /2    ᫥
⠢  RPLY    ᭨      ࠭    DIN.  १  /2  ᫥
 DIN    ⠢    設  ⨢  ᮪      
뢠 SYNC. ᫨ AR        ᨣ  SYNC      뫮  ᮢ
אַ 㯠,    ᫥    SYNC  ⠢      横
᫥饣    ,    ᫨        ନ஢    ஬.    ᫨
ந室 楤  ⥭    ⥬  (⮩)  ,  SEL    䠧
뤠    뤠    ஢    ᮢ        ६    
ᨣ  設 -.
	楤    ਬ                   
ॣ  譥  ன⢠.    뤠    ⠪  ,      
  ᭮  .  ᫥   뤠        ᨣ        室
ࠫ  室    ⨢  ᮪    ⥬      ᨬ    
⮤  樨  १  1.5    3.5    設   ⠢    .
१  ᫥  뤠      뢮  DOUT      ஢.
᫥  室  RPLY    稢  ,  ᭨  ᭠砫  DOUT,
⥬ १ /2        १  /2  SYNC.  ᫨  RPLY    ⠢
   64    ᫥  ⠢  DOUT,    ᭨  DOUT,SYNC  
    ࠫ    뢠    ᠭ.  ⮡  ࢠ  
室 RPLY    ⨥  DOUT    ,  RPLY    ⠢  
    䠧  ᮪  ஢  CLCO.  ᫨  AR       ࠭
SYNC,      뫮    אַ  㯠,  १  /2    ᫥    
    ⠢    設      横  ᫥饣  .
 楤   WTBT  뤠    ஢    䠧  뤠  .
  ஢  뤠  SEL  䠧  뤠         饭    
⥬  .    䠧  뤠    WTBT  뤠     ஢
        ᮪       ᫮.        ६    WTBT
ᮢ    ᨣ     뢮  -.
	⥭-䨪-  ⮨      䠧:  뤠    ,
⥭    .  뤠          ᭮  .   
⥭-   ᭮  ⥭,    ᪫祭  ⮣,    ᫥  
DIN    뢠  SYNC.      稭  ⮫쪮  ᫥   ⮣,
  㤥    RPLY  䠧  ⥭.    ࢠ     ⨥
DIN    ⠢      䠧       ࠢ    3.    ⮡    
ন  楤  ,  RPLY             ।    ⮣
ࢠ. 믮  䠧  ,  砭  横      室  
᫥饬  横  筮  ⠪,      筮  .  WTBT   뤠
᮪  ஢    䠧  뤠      䠧  ⥭.    䠧   
筮 筮  .  AR        室    䠧  ⥭  
䠧 ,       ⮫쪮    砫  ᫥饣  .  SEL
뤠      䠧  뤠  ,  ᫨          ⥬
.
	ਥ      뢠        ⠢    
ࠡ⪨ ୮  뢠    ᨣ  VIRQ.      ஢  
VIRQ,  ᫨  뢠       ᪨஢        ࠫ    ᢮,
    稭    楤    ࠡ⪨    뢠.     -(SP)<-PC,
-(SP)<-PSW,    ⥭      뢠:  ⠢    DIN
  १    ᨣ  IAKO.      RPLY    祭  64      ᫥
⠭  DIN,  ᫨    襫,    뢠      ᠭ.    ᫥
室  RPLY    믮  ⥭    ᭨  DIN.  ॡ   
⠢    ⭮⥫쭮  RPLY      ⭮⥫쭮  DIN   ⠪
,   ᭮ ⥭.  SYNC,  WTBT,  SEL    ਥ    


室    ᮪  ஢.  AR    ⢮.    砫    ᫥饣
 । ⨥  RPLY.    ⮣,  ⮡    ⨥  DIN  
砫  뤠      ᫥饬  横        뫠    쭠
প,  RPLY        ,  祬  १  2  ᫥    DIN.
VIRQ          㧪    PSW,       ਬ
        뢠.  ਥ            뢠
 ᮡ  ᭮ .

	।⠢ :
襭    אַ         ।⠢    ᫥    
横       ࠫ,  ᨬ      ,    ⮬
᫥      ६  ࠡ⪨  뢠.  DMR   ਭ    ஬
    ஢  CLCO.  DMGO  뤠    䠧    ஢    CLCO.
᫨              㯫  DMR,       १
1..1.5    ᫥  DMR    ᯠ  CLCO  ⠢    DMGO    .    ᫨
  ࠭  室  DMR  砫  ,  ..  ⠢        
᭮   DIN  ᭮ ( ..   ⥭   )
  믮            ࠧ襭    אַ    
砭 . DMGO  ⠢    ⮬  १    ᫥    DIN
  楤  ⥭    १  1.5    ᫥    DOUT      楤
    ⥭-䨪樨-.  ᫥    楤    ⥭    
  뢠  DMGO  㤥  ⠢    ,  祬  १  1.5  
᫥    RPLY.    祭  DMGO  ன⢮        ⠢
SACK  ⥬   DMR.    ᭨  ᨣ  DMGO      ஢
CLCO     ᨣ  SACK    প      ,    
  DMR  १  0.5-1.5  .  ६    ⠭  DMGO  
ॢ   ﭨ SYNC,  DIN,  DOUT,  WTBT,  AD0-AD15.  ⮡  
室  ⠫  ⨢묨,        SACK,  RPLY,  AR.  ᫥
᢮  ࠫ  ன⢮    稭   뤠    
।      ,  祬  १  1.5    ᫥    ᫥
 . 
	᫨            ᮢ,  ⢥   
  (  W1:160000..163777;  W2:164000..167777  ),  ,  ०    祬
  ,  ⠢      WRQ1/WRQ2.  ᫨      ᢮,
  奬  㦨      ⠢    WACK.   쪮
᫥  祭  ⮣  ᨣ    筥  横    .    ⮡
饭    ᭮  ࠭      ⫨砫       ⠫쭮
,    WACK  ᮥ     .        ⮬        
믮    ࠧ,    ᨣ  WRQ      .    WRQ
⠢ ஬    䠧    CLCO,  WACK  ਭ    䠧
  CLCO.    ,  祬  १    ᫥    WACK   
᭨ WRQ   䠧  ᮪  CLCO    稭  楤      
  ᫮  砭  ।饣  .  ᫨  ।騩       
襭,        ⪫뢠      襭.  WACK  
᭨    1.5    ᫥  SYNC  楤      .  
DMR      ᮪  ਮ,  祬  ᨣ       .    
        ᯮ짮  室  WIR:    室      
 ந ᮪ਮ⭮ ᪨㥬 뢠.


#!#	    ࠧ    奬                ᮡ⥩:#!#
-  楤  ⥭      ⠢  DIN      
  ࠫ      室        "襭"    ﭨ.
⥣᪨  頥      ६  稥      ᪮
;
-  楤        ⥭-䨪-        ।
஭    ,  ᨣ  DOUT,WTBT  ⭮⥫쭮    䠧    CLCO;
-  室  RPLY  室  ᯥ  ਢ離    ᨣ        奬:
	SACK,RPLY १ १  1..3   +5;
	אַ 室 5332 (뢮 9)  RPLY (뢮 27);
	SACK ᮥ  室 S 2 (뢮 10);
	CLC (20- 뢮)   室 C 2 (뢮 11);
	RPLY   室 D 2 (뢮 12);
	 室 R 2   (뢮 13);
-  楤         ࢠ    ६    ᠭ
  ⠢ SYNC;
-뢠    ᨣ  WIR  ४頥  믮        
䠧,  뢠  ࠡ  ᨣ  饣        ७    
    ।  ࠢ        250    ࠭
 ⥪ ⥪饣 ﭨ . 
	⥫쭮  WIR          4,  ⨢  -  ,
ࠡ⪠  뢠  ந室  ᫥       ᨣ    (室    
᮪  ஢).

		楤 砫쭮 ᪠.
	砫    ᨣ      ஢.  ᫥  祭   ⠭
 ࠭, 祬 १ 40    ॢ  DCLO    ᮪  ஢.    
DCLO  INIT  㤥  ⠢  ᮪  ஢.        祬  १
70      ACLO,    ⮬  筥  ࠡ  யணࠬ  ᪠    
  筥      ࠫ.    ६    ஢   DCLO
   뢠        砫쭮    ﭨ    ७    奬.
᫥    ACLO    ⠥    ॣ  (SEL),    ⥬
ନ           砫쭮    ᪠    (15..8)=SEL(15..8),
(7..0)=0.  PC<-(),  PSW<-2(),  ஢    筨    뢠,
  ᫨    ᪨஢,    뢠,  ᫨  ,      㧨
।   稭 믮.


			PSW.

	PSW ᮤন ଠ  ⥪饬 ﭨ .
	.	ᠭ
0	C	carry-७, ⠭, ᫨  ७  
		ᠬ 襣 ࠧ鸞   ᤢ  । 
		ࠧ來 ⪨ 뤢㫠 窠
1	V	overflow-䬥᪮ ९
2	Z	zero-㫥 १
3	N	negative-⥫ १
4	T	trap- ஢. ᫨ "1",  뢠 
		14 祩 ᫥  .
5,6		 ᯮ
7	Prty	ਮ .
8	H	halt-ਧ ⮢ ०.

	 ० HALT (H=1)  ६ 뤠      ࠫ  뤠
  ஢  SEL.    樨  祭  ⠭,  ⠫  ﭨ
  믮    HALT  (ࠡ⪨  ᨣ  HALT)  ᫥    㧪


PC    PSW  ந室  ਭ㤨⥫쭠  ⠭  H=1      ⮣,    ⮡
㧨    祭  PC    PSW    ᭮  ࠭⢠    ०
HALT.  ⥫쭮  ०   ࠡ        ।    祭
㦠 ᫮ ﭨ. 

,뢠	PSW

MTPS			PSW(7..5,3..0)	load
			PSW(4,8)	keep

RTI,RTT			PSW(7..0)	load
			PSW(8)		keep,if new PC<160000
			PSW(8)		load,if new PC>157777

TRAP,IOT,EMT,		PSW(7..0)	load
vector interruptions	PSW(8)		zeroed

power on,fatal errors	PSW(8..0)	load
HALT,STEP,START


	    㧪            FIS:    뢠
  ॣ,  ᫨  SEL(7)=1,    TRAP  TO  10,  ᫨    ,    
室    ०   HALT                (15..8)=SEL(15..8),
(7..0)=00001000.
	  믮    ०    HALT    .        ᠭ
⥬ .
	뢠  ந室  ⮫쪮     砭    ⥪饩    .
쪮  ᠭ  뢠        ⠤        믮.
筨  뢠:   १ࢭ    ,    饭        (।
ࠢ      ॣ  饣  祭),   ᠭ,    -,
  ஢  HALT    VIRQ,  ⥫  ஭  ACLO,  EVNT,    WIR.
⠭    ⪠        ⮫쪮    믮  RTT,  RTI,
STEP, START      㧪    뢠.  ᫨      ⠭
  㧪    뢠,    ࢮ  뢠    ⨮  
ந    믮   ࢮ            .    ᫨
᫥   RTI,  RTT    -,  ᫥  믮  
ந 뢠   ,      ⥪  ࠭  PSW    饭  -
ࠧ冷.  㥬    START,  STEP    ,  ᫥  믮
뢠    ந室.  START,  RTI  ⠢  ,        믮    -
뢠.    뢠    HALT    ,    뢠    .
뢠    HALT  ⠭           믮    뢠.
  믮  㥬  -ᠭ,       PSW        :
뢠  㤥. WAIT   .

	ਮ 뢠:
		
		࠯  10
		WIR
		T
		ACLO
		 HALT
		EVNT
		VIRQ


	  -ᠭ        யணࠬ    楤
ࠡ⪨ 뢠.
PSW bit		᪨
87		
00		 ᪨஢
01		EVNT,VIRQ
10		HALT
11		HALT,ACLO,EVNT,VIRQ

 ० USER PC', PSW' 㡫 ᭮.
 室   HALT    ⠭    7  PSW    ࠦ  
  7  8.

筨		࠭ ﭨ ।襣 

,.	004		⥪
१.	010		⥪
-,BPT	014		⥪
IOT		020		⥪
ACLO		024		⥪
EMT		030		⥪
TRAP		034		⥪
EVNT		100		⥪
WIR		250		⥪
VIRQ		 	⥪
ਬ砭:	  १ 訥    VIRQ.

power on	***000		
  HALT	***004		PC',PSW'
१.  HALT	***010		⥪  halt
-,BPT  HALT***014		⥪  halt
IOT  HALT	***020		⥪  halt
ACLO  HALT	***024		⥪  halt
EMT  HALT	***030		⥪  halt
TRAP  HALT	***034		⥪  halt
EVNT  HALT	***100		⥪  halt
HALT,HALT	***170		PC',PSW'
 	***174		PC',PSW'
WIR  HALT	***250		⥪  halt
 ਥ 	***274		PC',PSW'
VIRQ  HALT	 	⥪  halt

***=SEL(15..8); 
ᯮ짮  ⪨  ࠧ鸞  ࠧ襭  뢠    CSR    ன⢠
  맢  ᠭ  ,  ᫨        믮    ⮩    
ந諮    뢠        ⮣    ன⢠.    ⮡      :

	MTPS	#200
	CLR	@#ॣ_ன⢠
	MTPS	#0


18012

孮 n-MOS; ॡ塞 譮 1.75 .
 ⠫ࠬ᪨ 40-뢮 2123.40-6

	:

1	0V	騩 ᨫ⥫ 設 -
2	AD7	7 ࠧ 設 -, ⨢-
3	AD6	6 ࠧ 設 -, ⨢-
4	AD5	5 ࠧ 設 -, ⨢-
5	AD4	4 ࠧ 設 -, ⨢-
6	AD3	3 ࠧ 設 -, ⨢-
7	AD2	2 ࠧ 設 -, ⨢-
8	AD1	1 ࠧ 設 -, ⨢-
9	AD0	0 ࠧ 設 -, ⨢-
10	WRQ(L)	    ୮ 
11	WAKI(L)	ࠧ襭   
12	DMR(L)	 
13	SACK(L)	⢥ত 墠 設 
14	DMGO(L)	ࠧ襭 
15	CLCO	室 ⠪⮢  F(CLCO)=1/2F(CLCI)
16	CLCI	室 ⠪஢
17	RPLY(L)	⢥ ன⢠
18	DOUT(L)	ᮯ஢ 
19	WTBT(L)	/
20	0V	騩 ७ 奬 
21	SYNC(L)	ᨭᨣ 
22	DIN(L)	ᮯ஢ ⥭
23	AR(L)	 ਭ
24	IAKO(L)	ࠧ襭 뢠
25	ACLO(L)	 ⥢ ⠭-᪨㥬 뢠
26	DCLO(L)	 +5V-  奬 
27	INIT(L)	 譨 ன
28	VIRQ(L)	 ୮ 뢠
29	HALT(L)	४⥫ ࠡ/. 뢠  HALT-.
30	EVNT	뢠  ⠩ (஭⮬)   100(octal)
31	SEL(L)	롮 ᭮ ॣ/饭  ⥬ 
32	AD15	15 ࠧ 設 -, ⨢-
33	AD14	14 ࠧ 設 -, ⨢-
34	AD13	13 ࠧ 設 -, ⨢-
35	AD12	12 ࠧ 設 -, ⨢-
36	AD11	11 ࠧ 設 -, ⨢-
37	AD10	10 ࠧ 設 -, ⨢-
38	AD9	9  ࠧ 設 -, ⨢-
39	AD8	8  ࠧ 設 -, ⨢-
40	+5V	⠭

	⫨  18062:
室 ⠪⮢    ࠢ    室.  ᨬ쭠  ⠪⮢
  (室!) ࠢ 10  ,  ॠ쭮    12-15  
襩 ଥ 室 ⠪⮢  ᨣ.  ᯮ⭮  த⢨  1.
ॣ஢ ᫮  ᥪ㭤, ॠ쭮  2.5 . ᯮ⭮ த⢨
    㬭    100000    /.    室             -;
  :  160000-163777;  室  뢠            ;
  ६  ⠩-⮢   設:    ᠭ    ࠫ    
᫥ 54 ⠪⮢ ;  楤  ᭮  ⥭:  3⠪-⥭,
⥬  6  ⠪⮢  設  ᢮,  ⥬  뤠    ᫥    
( 2 ⠪  ).    ନ஢      室


      㭠ࠢ  뢮  ⥭樠  3-3.5  ⥫ﬨ  
ᮯ⨢ 2-560    ᨬ      㧪    ⠪⮢
.  ᮯ⨢ ⥫ 560  ७      ⥭樠
  ॢ蠫 0.5.   ࠢ 뤥ন  ⪮  몠
ந쭮 筮 뢮      ஢  ⠭  (0,+5);
      ᫥  ஢      㤠    릥
  쭨  (40,220);              
孮᪠ 頤-뢮 . ଠ쭮 殮     
-2, ७  ਡ஬    室  ᮯ⨢  1.    祭
ᨬ쭮 த⢨ ( 2 /)  ॡ 
  訬  ஢    ⮩  蠤  ࠬ᪨      47.
     祭  ⥫쭮  ᬥ饭  
 ( 1.5 ),   ਢ    ॣॢ      ⠪⮢
    50%-75%    ᨬ쭮.  祭      
  騬 ஢ 㢥稢 ᬥ饭        15-20%.  
饥 ६ ᪠  㯯          ⠪⮢  :
㯯   10   㯯   8    CLCO    .    㯯  
ન  窮                    ⮢.    
祭  ⥬   FIS  (  䬥⨪)  ४
ᯮ짮   18012.055,      ᯮ      140000.  
ଠ쭮 ࠡ ணࠬ  ⮣    㦭  稥    1    
 160000   ⮢  .        ⠪  室  
⮢ . ணࠬ 稪  ९뢠  ।  ᪮  
 010000q  짮⥫᪮  .  ६  ࠬ  ஢  
⠭  䥩ᮢ   䠩 INTERF.HLP.



			        

	   PDP11 -  


	ᠭ  ⥬      PDP11-ᮢ⨬    設    ⠢
    ᭮:    ᠭ    ⥬               "஭-60",
㬥 "ணࠬ ᯥ祭   3: . ᠭ  몠.",
ࠢ筨  । ,  ࠢ筨  "ய    ய
 ⥣ࠫ 奬"  ।. .. 孮, .2 .   
 㣨 筨.

		祭  ⥪:
	*   -0  ᫮, 1  
	ss  - 筨 (6 )
	dd  - ਥ (6 )
	R   -ॣ 饣 祭 (3 )
	xx  -ᬥ饭 (8 ), +127 .. -128
	n   - (3 )
	M   -᪠ (4 )
	nn  -᫮(6 )
	\   -१ࢭ/ 
	eis -EIS 
	fis -FIS 
	fpu -FPU 
	cis -CIS 
	?   - ࠭᫨  MACRO-11 [61], ᠭ  
	::  - 稥-ந쭠 (쬨筠) 
	mmg - ᯥ 
	si  -ᯥ樠쭠 : 㭨쭠  㪠 
	⠭  ᫮:
	-   - 
	1   -ᥣ ⠭  1
	0   -ᥣ 頥
	*   -⠭/  ᮮ⢥⢨  騬 ࠢ:
	     N -⠭, ᫨ 訩  १ ⠭,
		 ;
	     Z -⠭  㫥 १,  ;
	     V -⠭  䬥᪮ ९,  
		;
	     C -⠭  ७  襣 ࠧ鸞,  
		頥;
	+   -⢨  ⮬ -  ᠭ ⭮ 樨.

	Last correction : Date 15/05/90  Time 02:24:55
 

op.	op.    instr.  PSW(CC)
code	name	set	NZVC	description

000000	HALT		----	뢮       ⨢    ०:
				뢠   믮        ⥪饩
				ணࠬ,  PC  㪠뢠    ᫥   
				ࢠ  ,  PC   ⮡ࠦ    
				᮫, ࠧ襭 ࠡ ᮫.   ࠧ
				 ॠ ࠧ筮:18011,2,3,
				1811  ॢ    ணࠬ    㦨
				⠭. 
				    18011     (177716)<-000010!(177716),
				(177676)<-(PSW),(177674)<-(PC),(PC)<-(160002)
				(PSW)<-(160004);
				 2   짮⥫᪮  ०  뢠
				뢠   HALT     ⠭,
				    HALT  ࠧ襭  HALT,  
				饭 믮    NOP.    㣨
				: ᫨   ᯥ  ,  
				  ᮮ⢥     ⠭⠬
				DEC,  ⠭,    
				१饭    窨  ⠭,        
				࠭             ⮢
				४⥫; ᫨   ᯥ  ,
				  믮﫠      KERNEL,  
				ந室  뢠    室      
				KERNEL    १ࢭ  樨;      
				KERNEL ⠭ ,  ᫨    
				1801/06 3.      HALT      KERNEL
				ॢ         HALT:    ⥪
				⮢  ⠭   100000
				      ⥪     PC,    PSW;
				㦠  PSW  ⠭⮩   340,    砥
				ᯥ   ८ࠧ ᮢ  
				22-ࠧ來     0 ⮢
				 (⮣  짮⥫).

000001	WAIT		----	    뢠.   
				⠭     ᢮    ⥬
				ࠫ    ࢮ    ᪨஢
				뢠.  PC  㪠뢠    ᫥  
				WAIT . ᫥      뢠
				믮    ணࠬ    த    
				᫥饩  WAIT .

000002	RTI		++++	    뢠.PC<-(SP)+,PSW<-(SP)+,
				㧨   㯭    ᫮  ﭨ
				 ⥪:
				 18012   H  㧨  ⮫쪮    
				HALT    室    HALT    USER

000003	BPT		++++	⫠筮  뢠        14    祩.
				-(SP)<-PSW,  -(SP)<-PC,  PC<-(14),  PSW<-(16)
				n,z,v,c: 㦠   뢠

000004	IOT		++++	ணࠬ  뢠  -뢮    20
				祩.  -(SP)<-PSW,  -(SP)<-PC,    PC<-(20),
				PSW<-(22);  n,z,v,c:        
				뢠;   ਬ    맮
				楤 -뢮 IOX    䮫筮
				樮 ⥬   ॣ樨 訡
				 ᪮ 樮 ⥬.

000005	RESET		----	  譨    ன.    ࠬ,
				騬    ᯥ    ,        
				USER  /  SUPERVISOR  ᯮ      NOP.
				⠢ ᨣ    譨  ன
				 ࠫ. ६  믮    
				⨯       ⠪⮢  .

000006	RTT	eis	++++	筠 RTI,   ⠭    T
				 PSW 뢠 ᫥       
				砭  ᫥饩  .

000007	MFPT	?		⥭  

000010	START	si	++++	18012    筮  ०  TRAP  TO  10,  
000011	START	si		halt  -  ०  PC<-PC',PSW(8-0)<-PSW'(8-0),
000013	START	si		᫨    IRQ,  稭  㧨      
				믮 . ᯮ    ४祭
				HALT->USER.
000012	START	si		    18012,   祭
				⢨  18011:(177716)<-177767&(177716)
				(PC)<-(177674),	(PSW)<-(177676)

000014	STEP	si	----	18012    筮  ०  TRAP  TO  10,  
000015	STEP	si		halt - ०  PC<-PC',  PSW(8-0)<-PSW'(8-0),
000017	STEP	si		᫮  ।    ࠢ    
				  PC,⥬ 㦨  뢠,
				譨   HALT  ⮬ ᫥.
000016	STEP	si		    18012,   祭
				⢨  18011:(177716)<-177767&(177716)
				(PC)<-(177674), (PSW)<-(177676)
		
000020	RD	si	**--	18012 ᭮ ⥭ (ᮡ    
				ࠫ,    ॡ  ⢥    RPLY    )
				R0<-(SEL) ⮫쪮  ⮢ ०

000021	URD	si	**--	18012  ⠥  ᫮   ࠭⢠ USER: 
				R0<-(R5)+ ⮫쪮  halt- ०.

000022	RDPC	si	**--	18012 ⥭   PC: R0<-PC',  ⮫쪮  
000023	RDPC	si		⮢ ०.

000024	RDPS	si	**--	18012 ⥭  PSW: R0<-PSW', ⮫쪮  
000025	RDPS	si		⮢ ०
000026	RDPS	si
000027	RDPS	si

000030	RD	si	**--	18012  ᭮  ⥭  筮 
				000020

000031	UWR	si	**--	18012   ᭮  ࠭⢮ USER:
				R0-> -(R5) ⮫쪮  ⮢ ०.

000032	WRPC	si	**--	18012    PC: R0->PC', ⮫쪮  
000033	WRPC	si		⮢ ०.

000034	WRPS	si	++++	18012    PSW: R0->PSW',  ⮫쪮 
000035	WRPS	si	****	 ⮢ ०
000036	WRPS	si
000037	WRPS	si

00004:		\
00005:		\
00006:		\
00007:		\

0001dd	JMP		----
				室. 㧨 PC    筨,  ᯮ
				  dd.    樨  0    (⪠
				믮  ,  ᠭ     ॣ
				饣  祭)    設⢥    ⨯
				஢ ਢ  TRAP TO  4;  PC<-(dst)

00020R	RTS		----	    ணࠬ. PC <- R, R <- (SP)

00021R		si	----	LSI-11:  祭  ७
				16-ࠧ來    ॣ஢:       (R)<-(R)+12;
				ᮤন  祭   祥:
				(R): RBA  -  ॣ    設.  ন
				᫥  設, ᯮ짮    
				祭 樨,   ०  -
				樨 ࠭ 祭 3,5,6,7; 
				(R)+2: RSRC  -  ॣ  室  ࠭,
				ᮤন    ᫥    室     ࠭
				宯࠭   樨.        ०
				樨 筨 0 訩   
				;
				(R)+4: RDST - ॣ ࠭  祭  -
				ᮤন  ᫥    ࠭    祭,
				祭 ஬;
				(R)+6: RPSW - 訥 4   -    ⮢
				4 - 7 ᫮ ﭨ ,  ⠫-
				;
				(R)+10: RIR - ॣ 樨  -  ᮤন
				⥪,    ।  ,  
				ଠ  36R  -  ᮡ⥩   ப.

00022n		si	----	LSI-11: । யணࠬ  ࠢ
				祩 3000; ᫨ ⠪ 祩 ,
				뢠  १ࢭ 樨.

00023n	SPL	mmg	----	⠭  ਮ  .  쪮  
				  KERNEL:  PSW(5-7)<-n;       USER,
				SUPERVISOR ᯮ  NOP.

000240	NOP		----	祣  , 筥    
				᫮  PSW (M=0, . ᫥. ).

00024M	CL<NZVC>	++++	    PSW(N,Z,V,C)    ᪥     4
				 ⮢  .
000241	(CLN)			(M=^B1000)
000242	(CLZ)			(M=^B0100)
000244	(CLV)			(M=^B0010)
000250	(CLC)			(M=^B0001)
000257	(CCC)			(M=^B1111)

000260	NOP'		----	  㯮, 祣  ᮤঠ⥫쭮
				 ,   000240 ⫨砥  ⥬,
				 ⠭    ᫮  PSW
				(M=0, . ᫥. ).

00026M	SE<NZVC>	++++	⠭  PSW(N,Z,V,C)  ᪥  4
				 ⮢  .
000261	(SEN)			(M=^B1000)
000262	(SEZ)			(M=^B0100)
000264	(SEV)			(M=^B0010)
000270	(SEC)			(M=^B0001)
000277	(SCC)			(M=^B1111)

0003dd	SWAB		++00	 ⮢  ᫮:byte1/byte0<-byte0/byte1
				n,z  ⠭     襬    
				१

0004xx	BR		----	室 ᫮. 饭 xx ⮬-
				 㬭  2,    ᪫뢠n    PC:
				PC<-PC+(2*offset)

0010xx	BNE		----	室   :
				PC<-PC+(2*offset) if z=0

0014xx	BEQ		----	室  
				PC<-PC+(2*offset) if z=1

0020xx	BGE		----	室    ࠢ
				PC<-PC+(2*offset) if n xor v =0

0024xx	BLT		----	室  
				PC<-PC+(2*offset) if n xor v =1

0030xx	BGT		----	室  
				PC<-PC+(2*xx) if z!(n xor v) =0

0034xx	BLE		----	室    ࠢ
				PC<-PC+(2*xx) if z!(n xor v) =1

004Rdd	JSR		----	室  ணࠬ: -(SP)<-R,R<-PC,
				PC<-(dst) 

*050dd	CLR(B)		0100	㫥 ਥ: (dst)<-0

*051dd	COM(B)		**01	⮢ ஢ ࠭:
				(dst)<-~(dst)

*052dd	INC(B)		**+-	ਡ  1    ࠭:  (dst)<-(dst)+1;
				v  ⠭  ᫨   (dst)    ॢ蠥
				077777,  

*053dd	DEC(B)		**+-	⠭  1    ࠭:   (dst)<-(dst)-1;
				v ⠭, ᫨  (dst)  뫮  100000,
				 .

*054dd	NEG(B)		**++	  筨          1
				(     ᫠):    (dst)<-    -(dst);
				v ⠭, ᫨ १ ⠫ 100000
				  ;  c    ᫨   祭
				१ 0,  ⠭

*055dd	ADC(B)		**++	ਡ    ࠭    ७ (
				    䬥⨪):        (dst)<-(dst)+c
				v ⠭, ᫨ (dst)  077777   c
				 ⠭,  ;
				c ⠭, ᫨ (dst)  177777   c
				 ⠭,  

*056dd	SBC(B)		**++	⠭  ࠭  ७ (
				 䬥⨪): (dst) <- (dst) - c
				v=1 ᫨ (dst)  100000,  ;
				c=1 ᫨ (dst)  0  c  ⠭

*057dd	TST(B)		**00	⠭ ⮢ ᫮ PSW , ᮮ⢥
				࠭

*060dd	ROR(B)		**++	楢 ᤢ ࠢ: 頥  
				࠭    ࠢ; 訩 
				㦠   ७, 訩 , 
				뤢  ࠭, 㦠   
				७; v=xor(c,n).

*061dd	ROL(B)		**++	楢 ᤢ : 頥  
				࠭    ; 訩 
				㧨   ७, 뤢 訩 
				 㦠   ७; v-xor(c,n).

*062dd	ASR(B)		**++	䬥᪨ ᤢ ࠢ: ন 
				࠭ ᤢ    ࠢ;
				訩 ()  ⠥ ;
				 ७ 㧨 ᮤন 뤢⮣ 
				; v=xor(c,n).   ࠪ⮢ 
				 楫᫥  ࠭ , 
				⪮, 騬   ७.

*063dd	ASL(B)		**++	䬥᪨ ᤢ : ᮤন
				࠭ ᤢ    ,
				訩  , 뤨  
				㧨   ७; v=xor(c,n). 
				 ᬠਢ  楫᫥ 
				㬭 ࠭  2. 

0064nn	MARK		----	⪠ ⥪:
				SP<-PC+2*nn,PC<-R5,R5<-(SP)+;nn-᫮ 
				ࠬ஢.

1064ss	MTPS		++++	  ᫮ ﭨ: PS<-ss,    
				      .

0065ss	MFPI	mmg	**0-	뫠  ⥪ ⥪饩  ᫮  
				筨  ࠭⢠ 権
				।饩 .

0066dd	MTPI	mmg	**0-	뫠  ⥪ ⥪饩  ᫮  
				ਥ  ࠭⢮ 権 ।饩
				.

1065ss	MFPD	mmg	**0-	뫠  ⥪ ⥪饩  ᫮  
				筨  ࠭⢠  ।饩
				. ᫨ ᯥ   ᯥ稢
				⤥쭮 ८ࠧ  ࠭
				  , ⭠ MFPI.

1066dd	MTPD	mmg	**0-	뫠  ⥪ ⥪饩  ᫮  
				ਥ  ࠭⢮  ।饩 
				᫨ ᯥ   ᯥ稢 ⤥쭮
				८ࠧ  ࠭  
				, ⭠ MTPI.

1067dd	MFPS			⥭ ᫮ ﭨ: (dst)<-PSW;   
				       .

0067dd	SXT	eis	-+0-	࠭ :
				(dst)<-0 if n bit is clear
				(dst)<-177777 if n bit is set
				z set if n bit clear

0070dd	CSM	?

0071::		\

0072nn	TSTSET	?

0073nn	WRTLCK	?

0074::		\
0075::		\
0076::		\
0077::		\

*1ssdd	MOV(B)		**0-	뫪: (dst)<-(src); MOVB ss,Rn 
				(뫪  ॣ 饣 祭),
				⢥ । ⮢ 権,
				࠭   筨
				 襬  ਥ;  뫪
				  ॣ १ ᥣ 뫠 
				 訩  ॣ.  ⠫ 
				⮢ 뫪 ࠡ  ⠬  
				筮  ᫮  ᫮.

*2ssdd	CMP(B)		***+	ࠢ src  dst  ⠭  ᫮
				PSW: (src) - (dst); 
				v=1, ᫨ ࠭ 뫨 ࠧ ,   
				ਥ    ,    १
				(ࠧ  ࠭);  
				c=0, ᫨  ७  襣 ࠧ鸞, 
				 ⠭.
				   室 ࠭.

*3ssdd	BIT(B)		**0-	஢ઠ  dst  ᪥ src  . 
				᫮: (src)&(dst)

*4ssdd	BIC(B)		**0-	⪠  dst  ᪥ src:
				(dst)<-~(src)&(dst)

*5ssdd	BIS(B)		**0-	⠭  dst  ᪥ src:
				(dst)<-(src)!(dst)

06ssdd	ADD		****	dst<-src+dst;
				v set if both operands were of the same sign
				& the result is of opposite, else cleared

16ssdd	SUB		***+	dst<-dst-src; 
				v=1 if operands were of opposite signs
				and the sign of the source was the same
				as the as the sign of the result; cleared
				otherwise
				c=0 if there was a carry from MSB, else set


070Rss	MUL	eis	**0+	The contents of the dst. register & source
				taken as two's complement integers are 
				multiplied & stored in the dst. register
				and the succeeding register if R is even.
				If R is odd only the low order product is
				stored.

071Rss	DIV	eis	++++	The 32-bit two's complement integer in R
				and Rv1 is divided by the source operand.
				Division will be performed so that the
				remainder is of the same sign as the
				dividend. R must be even.
				N is set if the quotient <0; cleared 
				otherwise. Z is set if quotient =0; cleared
				otherwise. V is set if source =0 or if the 
				absolute value of the register is larger than
				the absolute value of the source. In this 
				case instruction is aborted because the 
				quotient would exceed 15 bits. C is set if 
				divide 0 attempted; cleared otherwise.

072Rss	ASH	eis	**++	The contents of the register are siifted
				right or left the number of times specified
				by the source operand. The siift count is 
				taken as the low order 6 bits of the source 
				operand. This number ranges from -32. to 31.
				Negative is a right siift and positive is a 
 

				left siift. The low order bit is extended
				when left siift; the high order bit extended
				when right siift.
				V is set if sign of the register chaned durin 
				siift; cleared otherwise. C is loaded from 
				last bit siifted out of reister.

073Rss	ASHC	eis	**++	The contents of the reister and the reister
				0Red with one is treated as one 32-bit word,
				R+1 (bits 0-15) and R (bits 16-31) are 
				siifted riht or left the number of times
				specified by the siift count. The siift
				count is taken as the low order 6 bits of 
				the source operand. This number ranes from 
				-32. to +31. Negative is a right siift and
				positive is a left siift. When the register
				chosen is an odd number the register 0R'ed
				with one are the same. In this case the right 
				siift becomes a rotate. The 16 bit word is 
				rotated right the number of bits specified
				by the siift count. The low order bit is 
				extended when left siift; the high order bit
				extended when right siift.
				V is set if if sign bit changes during the
				siift; cleared otherwise. C is loaded with
				high order bit when left siift, loaded with
				low order bit when right siift (loaded with
				the last bit siifted out of the 32.-bit 
				operand).

074Rdd	XOR	eis	**0-	᪫饥 '': (dst)<- R xor (dst)

07500R	FADD	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>
					operand B bits 16-31
					operand B bits 0-15
					result bits 16-31
					result bits 0-15
				result=A+B

07501R	FSUB	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>	operand B bits 16-31
					operand B bits 0-15
					result bits 16-31
 

					result bits 0-15
				result=A-B

07502R	FMUL	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>	operand B bits 16-31
					operand B bits
					result bits 16-31
					result bits 0-15
				result=A*B
				if the result <2E-128 then the result 
				is treated as zero.

07503R	FDIV	fis	**00	initial state:
				R=>	operand B bits 16-31
					operand B bits 0-15
					operand A bits 16-31
				(R)+6=>	operand A bits 0-15
				After operation floating point stack
				looks:
				R=>	operand B bits
					operand B bits
					result bits 16-31
					result bits 0-15
				result=A/B
				if the result <2E-128 then the result 
				is treated as zero.

07504:		\
07505:		\
07506:		\
07507:		\
 

076020	L2D0	cis

076021	L2D1	cis

076022	L2D2	cis

076023	L2D3	cis

076024	L2D4	cis

076025	L2D5	cis

076026	L2D6	cis

076027	L2D7	cis

076030	MOVC	cis

076130	MOVCI	cis

076031	MOVRC	cis

076131	MOVRCI	cis

076032	MOVTC	cis

076132	MOVTCI	cis

076033		\
076133		\
076034		\
076134		\
076035		\
076135		\
076036		\
076136		\
076037		\
076137		\

076040	LOCC	cis

076140	LOCCI	cis

076041	SKPC	cis

076141	SKPCI	cis

076042	SCANC	cis

076142	SCANCI	cis

076043	SPANC	cis

076143	SPANCI	cis

076044	CMPC	cis
 

076144	CMPCI	cis

076045	MATC	cis

076145	MATCI	cis

076046		\
076146		\
076047		\
076147		\

076050	ADDN	cis

076150	ADDNI	cis

076051	SUBN	cis

076151	SUBNI	cis

076052	CMPN	cis

076152	CMPNI	cis

076053	CVTNL	cis

076153	CVTNLI	cis

076054	CVTPN	cis

076154	CVTPNI	cis

076055	CVTNP	cis

076155	CVTNPI	cis

076056	ASHN	cis

076156	ASHNI	cis

076057	CVTLN	cis

076157	CVTLNI	cis

076060	L3D0	cis

076061	L3D1	cis

076062	L3D2	cis

076063	L3D3	cis

076064	L3D4	cis

076065	L3D5	cis

076066	L3D6	cis
 

076067	L3D7	cis

076070	ADDP	cis

076170	ADDPI	cis

076071	SUBP	cis

076171	SUBPI	cis

076072	CMPP	cis

076172	CMPPI	cis

076073	CVTPL	cis

076173	CVTPLI	cis

076074	MULP	cis

076174	MULPI	cis

076075	DIVP	cis

076175	DIVPI	cis

076076	ASHP	cis

076176	ASHPI	cis

076077	CVTLP	cis

076177	CVTLPI	cis

0762::		\
0763::		\
0764::		\
0765::		\

076600	MED6X	cis

076601	MED74C	cis

076602		\
076603		\
076604		\
076605		\
076606		\
076607		\
07661:		\
07662:		\
07663:		\
07664:		\
07665:		\
07666:		\
 

077Rnn	SOB	eis	----	R<-R-1; if not 0 then PC<- PC-2*offset

1000xx	BPL		----	室, ᫨ :
				PC<-PC+(2*offset) if n=0

1004xx	BMI		----	室,᫨ :
				PC<-PC+(2*offset) if n=1

1010xx	BHI		----	室, ᫨ :
				PC<-PC+(2*offset) if c=0 & z=0

1014xx	BLOS		----	室,᫨   ࠢ:
				PC<-PC+(2*offset) if c!z=1

1020xx	BVC		----	室,᫨  ९:
				PC<-PC+(2*offset) if v=0

1024xx	BVS		----	室,᫨ ९:
				PC<-PC+(2*offset) if v=1

1030xx	BCC		----	室, ᫨  뫮 ७:
1030xx	BHIS
				PC<-PC+(2*offset) if c=0

1034xx	BCS		----	室,᫨  ७:
1034xx	BLO
				PC<-PC+(2*offset) if c=1

1040::	EMT		++++	-(SP)<-PSW; -(SP)<-PC; PC<-(30); PSW<-(32)
1041::	EMT			n,z,v,c: loaded from trap vector
1042::	EMT
1043::	EMT

1044::	TRAP		++++	-(SP)<-PSW; -(SP)<-PC; PC<-(34); PSW<-(36)
1045::	TRAP			n,z,v,c: loaded from trap vector
1046::	TRAP
1047::	TRAP

107:::		\
 

code	name	       fpp(cc)	description
		      F(NZVC)

170000	CFCC	fpu

170001	SETF	fpu

170002	SETI	fpu

170003	LDUB	fpu

170004	LDSC	fpu

170005	STA0	fpu

170006	STB0	fpu

170007	STQ0	fpu

170010		\

170011	SETD	fpu

170012	SETL	fpu

170013		\

170014		\

170015		\

170016		\

170017		\

1702DD	STFPS	fpu

1703DD	STST	fpu

1704DD	CLRD	fpu
1704DD	CLRF	fpu

1705SS	TSTD	fpu
1705SS	TSTF	fpu

1706DD	ABSD	fpu
1706DD	ABSF	fpu

1707DD	NEGD	fpu
1707DD	NEGF	fpu

1710DD	MULD	fpu
1710DD	MULF	fpu

1714DD	MODD	fpu
1714DD	MODF	fpu
 

1720SDD	ADDD	fpu	***0	SUM=(AC)+(FSRC): if underflow occurs and FIU 
1720SDD	ADDF	fpu		is not enabled, AC<-exact 0
				if overflow occurs and FIV is not enabled,
				AC<-exact 0 on FP11C
				for all other cases, AC<-SUM
				The addition is carried out in single or 
				double precision and is rounded or chopped
				in accordance with the values of the FD and 
				FT bits in the FPS register. The result is 
				stored in AC except for:
				oerflow with interrupt disabled on the FP11C
				underflow with interrupt disabled.
				For these exceptional cases, an exact 0 is
				stored in AC.
				If FIVU is enabled, trap on -0 in FSRC
				occurs before execution.
				If overflow or underflow occurs and if the
				corresponding interrupt is enabled, the trap 
				occurs with the faulty result in AC. The 
				fractional parts are correctly stored.
				The exponent part is too large by 400 octal
				for underflow, except for the special case
				of 0, which is correct. If no errors occures,
				then for oppositely signed operands with
				exponent differences of 0 or 1, the answer
				returned is exact if a loss of significance
				of one or more bits occurs. Note that these
				are the only cases for which loss of 
				significance of more than one bit can occur.
				For all other cases the result is inexact 
				with error bounds of
				1 LSB in chopping mode with either single or 
				double precision.
				1/2 LSB in rounding mode with single 
				precision.
				9/16 LSB in rounding mode with double 
				precision.
				The undefined variable -0 can occur only in 
				conjunction with overflow or underflow.
				It will be stored in AC only if the 
				corresponding interrupt is enabled or, for 
				the FP11B, on overflow even if the overflow
				interrupt is not enabled.

1724SDD	LDD	fpu	**00	AC<-(FSRC)
1724SDD	LDF	fpu		load single or double precision number
				into accumulator. If FIVU is enabled,
				trap on -0 occurs before AC is loaded.
				Neither overflow or underflow can occur.
				These instructions are exact.
				These instructions permit use of -0 in a 
				subsequent floating point instruction if
				FIVU is not enabled and (FSRC)=-0.

1730SDD	SUBD	fpu
1730SDD	SUBF	fpu
 

1734SDD	CMPD	fpu
1734SDD	CMPF	fpu

1740SDD	STD	fpu	----	FDST<-(AC): store single or double number
1740SDD	STF	fpu		from accumulator.

1744SDD	DIVD	fpu
1744SDD	DIVF	fpu

1750SDD	STEXP	fpu

1754SDD	STCDI	fpu
1754SDD	STCDL	fpu
1754SDD	STCFI	fpu
1754SDD	STCFL	fpu

1760SDD	STCDF	fpu
1760SDD	STCFD	fpu

1764SDD	LDEXP	fpu

1770SDD	LDCID	fpu
1770SDD	LDCIF	fpu
1770SDD	LDCLD	fpu
1770SDD	LDCLF	fpu

1774SDD	LDCFD	fpu
1774SDD	LDCDF	fpu
 
